According to a new report from Taiwan, the Taiwan Semiconductor Manufacturing Company (TSMC) will commence mass production of its 2-nanometer semiconductor process in 2025. The timeline matches TSMC's schedule, which its management has provided several times during analyst conferences. Additionally, these rumors suggest that TSMC is also planning a new 2-nanometer node called N2P which will enter production in the year after N2. TSMC is yet to confirm a new process called the N2P, but it has used similar naming for its current 3-nanometer semiconductor technologies, with N3P being an enhanced version of N3 and reflecting refinements in the production process.
TSMC's Second Quarter Revenue Expected To Drop By 5% to 9% According To Morgan Stanley
Today's report comes from Taiwanese supply chain sources and shares that TSMC's 2-nanometer semiconductor mass production is on schedule. The company's executives have outlined the timeline for the next-generation manufacturing process several times, including during a conference in 2021 where the firm's chief executive Dr. C.C. Wei shared that his firm is confident about 2-nanometer mass production in 2025.
Since then, the TSMC's senior vice president for research and development and technology, Dr. Y.J. Mii, confirmed this timeline last year, and Dr. Wei's latest take on the matter came in January when he revealed that the process was 'ahead of schedule' and will enter the test production stage in 2024 (also part of TSMC's timeline).
The latest rumors build on these statements and add that mass production will occur at TSMC's facilities in Baoshan, Hsinchu. The Hsinchu plant is TSMC's first choice for the advanced technology, with the firm also building a second facility in Taiwan's Taichung sector. This facility, called Fab 20, will be built in phases and was confirmed by management in 2021 - when the company acquired land for the plant.
Another interesting tidbit from the report is an alleged N2P process. While TSMC has confirmed a high-performance variant of the N3, dubbed N3P, the fab is yet to provide similar details for the N2 process node. The supply chain sources suggest that N2P will use BSPD (back-side power delivery) to improve performance. Semiconductor fabrication is a complex process. While printing transistors that are thousands of times smaller than a human hair often gets the most attention, other equally complex areas limit manufacturers from increasing chip performance.
One such area covers the wires on a piece of silicon. The transistors have to be connected to a power source, and their minuscule size means that the connecting wires have to be equally smaller. A significant limitation that new process technologies face is the placement of these wires. The first iteration of a process generally sees the wires placed above the transistors, and later generations place them below.
The latter process is called BSPD, and it is an extension of what is dubbed in the industry as through silicon vias (TSVs). TSVs are connections that pass through a wafer and allow multiple semiconductors, such as memory and processors, to be stacked on top of each other. A BSPDN (back-side power deliver network) involves bonding the wafers to each other and creates power efficiencies as current is delivered to the chip via the much more suitable backside with lower resistance.
Although rumors suggest new process technologies, investment bank Morgan Stanley believes that TSMC's revenue will drop between 5% and 9% during the second quarter. The bank's latest report increases the expected drop, which had initially been expected to sit at 4% quarter over quarter. The reason behind the dip is an order cut down from smartphone chip companies,
Morgan Stanley adds that TSMC can reduce its full-year 2023 revenue guidance from 'slight growth' to flat and that its primary customer, Apple, will have to accept a 3% wafer price increase later this year. According to the research note, TSMC's yields for the N3 process node - used on the iPhone - have also improved.
Written by Ramish Zafar
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