Does The AMD Instinct MI300 Accelerator Have An Exascale APU Mode?

Twitter user ExecutableFix located something called "SH5". SH5 is speculated to refer to the new AMD Instinct MI300 accelerator— which is a successor to MI200.

There's a server socket called "SH5" that features CPU with CPUID 0xA80F00... called "MI300"

— ExecutableFix (@ExecuFix) September 16, 2021

Readers will remember that MI200 has yet to release. In fact, the new MI200 is slated to be released towards the end of 2021. This is why the new socket leak is under heavy speculation.

Inside the AMD Instinct MI200 is an Aldebaran GPU featuring two dies, a secondary and a primary. It has two dies with each consisting of 8 shader engines for a total of 16 SE's. Each Shader Engine packs 16 CUs with full-rate FP64, packed FP32 & a 2nd Generation Matrix Engine for FP16 & BF16 operations. Each die, as such, is composed of 128 compute units or 8192 stream processors. This rounds up to a total of 220 compute units or 14,080 stream processors for the entire chip. The Aldebaran GPU is also powered by a new XGMI interconnect. Each chiplet features a VCN 2.6 engine and the main IO controller.

As for  DRAM, AMD has gone with an 8-channel interface consisting of 1024-bit interfaces for an 8192-bit wide bus interface. Each interface can support 2GB HBM2e DRAM modules. This should give us up to 16 GB of HBM2e memory capacity per stack and since there are eight stacks in total, the total amount of capacity would be a whopping 128 GB. That's 48 GB more than the A100 which houses 80 GB HBM2e memory.

The MI300 is rumored to showcase four chipsets for GPUs, which happens to be twice the amount available for MI200. MI300 is not slated to release for another year or longer from other sources' estimations.

ExecutableFix also states that SH5 variants might include a Zen4 CPU chip in the same packaging, but again under speculation.

AMD discussed "Exascale APUs" in the whitepaper, "Design and Analysis of an APU for Exascale Computing." In the paper, AMD hinted at a high-performance APU design that "stacked HBM memory on top of GPU chiplets which would be combined with CPU chiplets," reports VideoCardz.

Two years ago, Twitter user Komachi found the first hint of AMD MI200 BIG APU mode in reference to the MI200.

What is BIG APU Mode for MI200?

— 遠坂小町@Komachi (@KOMACHI_ENSAKA) December 26, 2019

With this new rumor, it could mean something more along the lines of MCM GPUs attached to EPYC CPUs, processing information at the same time.

Source: ExecutableFix, Komachi, VideoCardz

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